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- [2] Package optimization of a stacked die flip chip based test package 6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004), 2004, : 590 - 594
- [3] Warpage Improvement for Large Die Flip Chip Package 2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 40 - +
- [4] Measurement of die stresses in flip chip on laminate assemblies PROCEEDINGS OF THE SEM IX INTERNATIONAL CONGRESS ON EXPERIMENTAL MECHANICS, 2000, : 609 - 615
- [5] Mechanisms of die and underfill cracking in flip chip PBGA package INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES AND INTERFACES, PROCEEDINGS, 2000, : 201 - 205
- [6] Effect of Flip Chip Package Architecture on Stresses in the Bump Passivation Opening 2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 936 - 942
- [7] Characterization of Moisture Induced Die Stresses in Flip Chip Packaging 2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, : 789 - 798
- [8] Lead Free Flip Chip Reliability for Various Package Types PROCEEDINGS OF THE ASME PACIFIC RIM TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC SYSTEMS, MEMS AND NEMS 2011, VOL 1, 2012, : 609 - +
- [9] Measurement of backside flip chip die stresses using piezoresistive test die 1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 : 298 - 303
- [10] Structural optimization of fine pitch, large die flip chip package 6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004), 2004, : 105 - 108