Random walk method for power grid noise analysis, that treats lots of large valued decoupling capacitors and calculates voltage drops from VCC, has been existing. The computational complexity of this method is O((LM)-M-2), where L is the number of interconnects and M is the transient analysis elapsed time. Therefore, when we apply the existing technique to actual circuit, it becomes very time consuming. This paper proposes a novel technique which improve the computational complexity from O((LM)-M-2) to 0(L). Basic idea is inversing the transient analysis timestep order from successor to predecessor that is backward direction. The CPU time using proposed technique can be 6 (%) and 12 (%) compared with existing technique and SPICE, respectively for one interconnect analysis.