Design and FPGA implementation of lattice wave fractional order digital differentiator

This paper deals with the design and FPGA implementation of a fractional order digital differentiator. It is realized using computationally efficient lattice wave digital filter (LWDF) which requires minimum multipliers in comparison to the direct form structure. A nature inspired ant lion optimization (ALO) algorithm is utilized to compute optimal coefficients of the LWDF based digital differentiator. The proposed LWDF based digital differentiator is compared with the existing literature in terms of magnitude response, percentage magnitude error and root mean square magnitude error. LWDF structure comprises of constant coefficient multipliers, adders and delay units which are implemented on FPGA with the help of Xilinx system generator for DSP design tool. For efficient implementation of multipliers, multiplier-less logic through digit recoding techniques such as canonic signed digit (CSD) representation and radix-2(r) encoding are described through Verilog HDL and incorporated in the implementation model as black box. Post-implementation results show that implementation based on the radix-2(r) encoding is found to be more efficient than that of the CSD encoding. The design and implementation results are also reported to highlight the improvements.