Ball grid array (BGA) solder joint intermittency real-time detection

被引：4

作者：

Roth, N. ^{[1
]}

Wondrak, W. ^{[1
]}

Willikens, A. ^{[1
]}

Hofmeister, J. ^{[2
]}

机构：

[1] Daimler AG, D-71059 Sindelfingen, Germany

[2] Ridgetop Grp, Tucson, AZ USA

来源：

MICROELECTRONICS RELIABILITY | 2008年 / 48卷 / 8-9期

关键词：

D O I：

10.1016/j.microrel.2008.07.064

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults ill solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain Sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods Of Stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Omega with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock - guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance. (c) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1155 / 1160

页数：6

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