A CHIP ARCHITECTURE FOR COMPRESSIVE SENSING BASED DETECTION OF IC TROJANS

被引：3

作者：

Tsai, Yi-Min ^{[1
]}

Huang, Keng-Yen ^{[1
]}

Kung, H. T. ^{[2
]}

Vlah, Dario ^{[2
]}

Gwon, Youngjune L. ^{[2
]}

Chen, Liang-Gee ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan

[2] Harvard Univ, Sch Engn & Appl Sci, Cambridge, MA USA

来源：

2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS) | 2012年

关键词：

Compressive sensing; IC Trojan; CS-JTAG; measurement generator; LEAKAGE POWER;

D O I：

10.1109/SiPS.2012.33

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a circuit under test (CUT). We describe our designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Our architecture achieves approximately a 10 x speedup and 1000 x reduction in output bandwidth while incurring a small area overhead.

引用

页码：61 / 66

页数：6

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