Along with the rapid spread of portable electronic products on the mobile computing market, the increase in the use of video streaming, photo sharing and also other data-intensive applications keep growing up continuously for now. More and more IoT/Wearable and 5G connectivity devices are required with Radio Frequency (RF) and Front-End Module (FEM) which has driven the development of IC packaging towards on small form factor, thin profile, better electrical and thermal performance, as well as 3D stacking for multi-function integration [1]. To approach these requirements, the System in Package (SiP) can be a combination of one or more chips plus optionally passive components by using Surface Mount Technology (SMT) and 3D structure of double side into a single package to offer a small form factor, high performance and systemization implemented. The high speed SMT process accomplishes the high-density with more than 50 discrete passive as well as active components and heterogeneous integration on package level approach. The development of double side technology offers the advantage of package size shrinkage by the same integrating discrete passive and active components layout. In this paper, the innovative packaging solutions of 3D double side SiP including the platform for both strip form of substrate base and wafer form of Fan-Out Redistribution Layer (RDL) base will be well introduced. Fan-Out RDL is an extension approach of Wafer Level Chip Scale Package (WLCSP), this technology is different from conventional wire bond or flip chip packages because the redistribution dielectrics and fine-line plated conductors are used for interconnection to replace the packaging substrates. As a case study, the calculation of 3D SiP package size can be shrunk around 50% area and the total package thickness can achieve around 15% z-height reduction with thin form coreless substrate and Fan-Out RDL technology utilization. The characterization analysis will apply simulation methodology for electrical comparison on DC resistance and parasitic inductance, thermal comparison on Theta JA (degrees C/W) and warpage comparison on the package structure of 3D double side SiP. Also, the typical reliability testing (Temperature Cycle Test, High Temperature Storage Life Test, Unbiased High Accelerated Stress Test) are built to verify 3D double side SiP structure for future IoT/Wearable and 5G devices application. Currently the market trends clearly drive towards 3D double side SiP, so this article illustrates the innovative packaging solutions with both substrate base and Fan-Out RDL base to provide a unique opportunity for enabling 3D integration and system in package.
