A low-jitter pulsewidth control loop with high supply noise rejection

被引：0
|
作者：
Liu, Shubin [1 ]
Zhu, Zhangming [1 ]
Gu, Huaxi [2 ]
Yang, Yintang [1 ]
机构：
[1] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China
[2] Xidian Univ, Sch Telecommun Engn, Xian 710071, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2013年 / 10卷 / 18期
基金：
中国国家自然科学基金;
关键词：
PWCL; low-jitter; noise rejection; voltage substractor; DCC;
D O I：
10.1587/elex.10.20130619
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-jitter pulsewidth control loop (PWCL) with high supply noise rejection for high-speed pipelined ADC is presented in this letter. Based on the edge triggered PWCL, An improved charge pump, a novel control stage (CS) and delay compensation circuits (DCC) was utilized to decrease the supply-induced jitter. The experimental results demonstrate that within 180 ns the PWCL can lock the clock duty cycles for the accuracy of 50 +/- 1% with 10%+/- 90% input duty cycle from 50 MHz to 500 MHz. The p-p jitter is 10.1 ps at 500 MHz, and the variation of duty cycle is less than 0.05% within +/- 10% supply noise.
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收藏
页数：6
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