Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling

被引：16

作者：

Chen, K ^{[1
]}

Hu, CM ^{[1
]}

Fang, P ^{[1
]}

Gupta, A ^{[1
]}

机构：

[1] ADV MICRO DEVICES INC, SUNNYVALE, CA 94088 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 1997年 / 18卷 / 06期

关键词：

CMOS integrated circuits - Electric current measurement - Gates (transistor) - MOSFET devices - Oxides - Semiconductor device models - Thickness measurement - Voltage measurement;

D O I：

10.1109/55.585355

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

MOSFET's and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 mu m have been studied at voltages from 1.5 V to 3.3 V, Physical and electrical measurement of gate oxide thicknesses are compared, Ring oscillators' load capacitance is characterized through dynamic current measurement, An accurate model of CMOS gate delay is compared with measurement data, It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted.

引用

页码：275 / 277

页数：3

共 5 条

[1] An accurate semi-empirical saturation drain current model for LDD N-MOSFET [J].