Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits

被引：0

作者：

Menon, SM ^{[1
]}

Jayasumana, AP ^{[1
]}

Malaiya, YK ^{[1
]}

机构：

[1] S DAKOTA SCH MINES & TECHNOL,DEPT ELECT & COMP ENGN,RAPID CITY,SD 57701

来源：

SIXTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1996年

关键词：

D O I：

10.1109/GLSV.1996.497622

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：214 / 219

页数：6

共 34 条

[21] TEST-GENERATION FOR I-DDQ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS
BOLLINGER, SW
MIDKIFF, SF
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (11) : 1413 - 1418
[22] Power-constrained testing for bridging and stuck short faults in CMOS combinational circuits
Ismaeel, AA
Bhatnagar, R
MICROELECTRONICS AND RELIABILITY, 1997, 37 (05): : 753 - 761
[23] Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults
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Borujeni, Shahram Etemadi
Ehsani, Mohammad Saeed
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, 28 (14)
[24] Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions
Mousum Handique
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[25] Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions
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Deka, Jantindra Kumar
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[26] A Diagnosis Pattern Generation Procedure to Distinguish Between Stuck-at and Bridging Faults in Digital Circuits
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Harish, S. P.
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Anita, J. P.
PROCEEDINGS OF THE 2019 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL SYSTEMS (ICCS), 2019, : 321 - 325
[27] Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits
Pomeranz, Irith
Reddy, Sudhakar M.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (02) : 333 - 337
[28] A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits
Biswal, Pradeep Kumar
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2023, 39 (03): : 323 - 346
[29] A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits
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Journal of Electronic Testing, 2023, 39 : 323 - 346
[30] DETECTION OF MULTIPLE INPUT BRIDGING AND STUCK-ON FAULTS IN CMOS LOGIC-CIRCUITS USING CURRENT MONITORING
JHA, NK
TONG, Q
COMPUTERS & ELECTRICAL ENGINEERING, 1990, 16 (03) : 115 - 124

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