Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits

被引：0

作者：

Menon, SM ^{[1
]}

Jayasumana, AP ^{[1
]}

Malaiya, YK ^{[1
]}

机构：

[1] S DAKOTA SCH MINES & TECHNOL,DEPT ELECT & COMP ENGN,RAPID CITY,SD 57701

来源：

SIXTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1996年

关键词：

D O I：

10.1109/GLSV.1996.497622

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：214 / 219

页数：6

共 34 条

[11] Internal feedback bridging faults in combinational CMOS circuits: Analysis and testing
Miura, Y
Seno, S
ETW 2001: IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS, 2001, : 9 - 16
[12] Test generation for current testing of bridging faults in CMOS VLSI circuits
Lee, T
Hajj, IN
38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1996, : 326 - 329
[13] Observation time reduction for IDDQ testing of bridging faults in sequential circuits
Higami, Y
Saluja, KK
Kinoshita, K
SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 312 - 317
[14] ON THE MODELING OF DIGITAL CIRCUITS FOR THE TEST PATTERN GENERATION FOR DEVICE INPUT FAULTS
DOKOUZYANNIS, SP
MICROELECTRONICS AND RELIABILITY, 1994, 34 (12): : 1923 - 1929
[15] On the modelling of digital circuits for the test pattern generation for device input faults
Dokouzyannis, Stavros P.
Microelectronics Reliability, 1994, 34 (12) : 1923 - 1929
[16] Minimal Test Set Generation for Input Stuck-at and Bridging Faults in Reversible Circuits
Handique, Mousum
Deka, Jantindra Kr
Biswas, Santosh
Dutta, Kamalika
TENCON 2017 - 2017 IEEE REGION 10 CONFERENCE, 2017, : 234 - 239
[17] GENERATING AN INPUT TESTS SEQUENCE FOR DETECTION OF SINGLE BRIDGING FAULTS IN COMBINATIONAL-CIRCUITS
DUBROVSKIJ, AV
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1980, (05): : 57 - 59
[18] GENERATING AN INPUT TESTS SEQUENCE FOR DETECTION OF SINGLE BRIDGING FAULTS IN COMBINATIONAL-CIRCUITS
DUBROVSKIJ, AV
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1980, (02): : 56 - 60
[19] I(DDQ) TESTING OF OSCILLATING BRIDGING FAULTS IN CMOS COMBINATIONAL-CIRCUITS
ROCA, M
SICARD, E
RUBIO, A
IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1993, 140 (01): : 39 - 44
[20] DESIGN AND TEST RULES FOR CMOS CIRCUITS TO FACILITATE IDDQ TESTING OF BRIDGING FAULTS
LEE, KJ
BREUER, MA
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1992, 11 (05) : 659 - 670

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