Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs

Achieving high reliability against transient faults poses significant challenges due to the trends of technology and voltage scaling. Thus, numerous soft error mitigation techniques have been proposed for masking Soft Error Rate (SER) in logic circuits. However, most soft error suppression approaches have significant overheads in terms of area, power consumption, and speed performance degradation. Herein, we propose two circuit-level techniques, namely Temporal Self-Voting Logic (TSVL) and Hybrid Spatial and Temporal Redundancy Double-Error Correction (HSTR-DEC), to prevent the effects of soft errors in logic circuits, occurring due to Single Event Upset (SEU) or Single Event Transient (SET). TSVL and HSTR-DEC circuits can be utilized to improve the reliability of a logic path with minimal impact on circuit delay while achieving a complete and cost-effective SEU handling as compared to traditional spatial or temporal redundancy approach. The primary contribution of the TSVL approach is that it eliminates error masking from the critical datapath, thus, area and energy overheads are significantly reduced. A transient gate-level fault injection and analysis is used to evaluate the capability of soft errors suppression of the proposed hardening approach. Experimental results indicate that TSVL can cover soft errors, on average, roughly by 99% while realizing an amelioration of 22.02% and 2.15% for area and speed degradation as compared to the previous Self-Voting DMR approach. Meanwhile, HSTR-DEC approach realizes a complete coverage for single and double SEUs while incurring comparable area and delay overheads as compared to the prior hybrid redundancy approach.