A hierarchical N-queen decimation lattice and hardware architecture for motion estimation

被引:34
作者
Wang, CN [1 ]
Yang, SW
Liu, CM
Chiang, TH
机构
[1] Natl Chiao Tung Univ, Dept Comp Sci & Informat Engn, Hsinchu 30050, Taiwan
[2] Natl Chiao Tung Univ, Inst Comp Sci & Informat Engn, Hsinchu 30050, Taiwan
[3] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30050, Taiwan
[4] Natl Chiao Tung Univ, Inst Elect Engn, Hsinchu 30050, Taiwan
[5] Inst Informat Ind, Multimedia Technol Lab, Taipei, Taiwan
关键词
decimation lattice; fast motion estimation; hierarchical decimation lattice; N-Queen pattern; pixel decimation; video coding;
D O I
10.1109/TCSVT.2004.825550
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A subsampling structure, an N-Queen lattice, for spatially decimating a block of pixels is presented. Despite its use for many applications, we demonstrate that the N-Queen lattice can be used to speed up motion estimation with nominal loss of coding efficiency. With a simple construction, the N-Queen lattice characterizes the spatial features in the vertical, horizontal, and diagonal directions for both texture and edge areas. Especially in the 4-Queen case, every skipped pixel has the minimal and equal distance of unity to the selected pixel. It can be hierarchically organized for variable nonsquare block-size motion estimation. Despite the randomized lattice, we design compact data storage architecture for efficient memory access and simple hardware implementation. Our simulations show that the N-Queen lattice is superior to several existing sampling techniques with improvement in speed by about N times and small loss in peak SNR (PSNR). The loss in PSNR is negligible for slow-motion video sequences and is less than 0.45 M at worst for high-motion estimation sequences.
引用
收藏
页码:429 / 440
页数:12
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