Concepts of Switching in the Time-Triggered Network-on-Chip

被引:34
作者
Paukovits, Christian [1 ]
Kopetz, Hermann [1 ]
机构
[1] Vienna Univ Technol, Real Time Syst Grp, A-1040 Vienna, Austria
来源
RTCSA 2008: 14TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS - PROCEEDINGS | 2008年
关键词
D O I
10.1109/RTCSA.2008.18
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered System-on-Chip (TTSoC) architecture. This includes the design of the switching components that make up the network-on-chip (NoC) as well as the switching algorithm applied in those components. Furthermore, we focus on the implications for the operation of the TTNoC entailed by these design choices, and deal with frequently used scenarios in a NoC, particularly multi-casting. Finally, we present results of a prototype implementation based on FPGA technology.
引用
收藏
页码:120 / 129
页数:10
相关论文
共 18 条
[1]   Xpipes: A network-on-chip architecture for gigascale systems-on-chip [J].
Bertozzi, Davide ;
Benini, Luca .
IEEE Circuits and Systems Magazine, 2004, 4 (02) :18-31
[2]  
Dally W., 2003, PRINCIPLES PRACTICES
[3]  
GELSINGER P, 2001, P SOL STAT CIRC C
[4]   AEthereal network on chip: Concepts, architectures, and implementations [J].
Goossens, K ;
Dielissen, J ;
Radulescu, A .
IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (05) :414-421
[5]  
HUBER B, 2008, THESIS TU VIENNA
[6]   Temporal composability [J].
Kopetz, H ;
Obermaisser, R .
COMPUTING & CONTROL ENGINEERING JOURNAL, 2002, 13 (04) :156-162
[7]   The time-triggered architecture [J].
Kopetz, H ;
Bauer, G .
PROCEEDINGS OF THE IEEE, 2003, 91 (01) :112-126
[8]  
Kopetz H, 2006, INT FED INFO PROC, V225, P105
[9]  
OBERMAISSER R, 2007, INT EMB SYST S IESS
[10]  
OBERMAISSER R, 2006, E I J J AUSTRIAN PRO, V3