Radiation Hardened Latch Designs for Double and Triple Node Upsets

被引：101

作者：

Watkins, Adam ^{[1
,2
]}

Tragoudas, Spyros ^{[2
]}

机构：

[1] Los Alamos Natl Lab, Los Alamos, NM 87545 USA

[2] Southern Illinois Univ Carbondale, Carbondale, IL 62901 USA

来源：

IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING | 2020年 / 8卷 / 03期

关键词：

Soft errors; radiation hardened latch; transient pulses; single event upset; double node upset; triple node upset; TOLERANT LATCH;

D O I：

10.1109/TETC.2017.2776285

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden latches against single event upsets (SEU). Currently, there has been a concerted effort to design latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant latch design. The latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant latch is 11.3 percent more power efficient than existing latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant latch. The TNU tolerant latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.

引用

页码：616 / 626

页数：11

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