Hardware implementation of a census-based stereo matching using FPGA

The real-time stereo vision is becoming important increasingly in the field of Robotics. It is very difficult to implement the real-time stereo vision system, because it requires very powerful processors. For solving this problem, we present the real-time hardware architecture of the census-based stereo matching IP (Intellectual Property) comprising support-weight and trellis dynamic programming structure. We use census-based cost that is robust for difference in brightness. Using Cost aggregation with support-weight window, our stereo vision system has more robustness for real environment. The stereo matching processor is implemented on a FPGA with the pre-processing part for the rectification and post-processing for reduction of noise. This stereo vision IP is implemented with HDL language and performed up to 30 FPS.