Hardware implementation of a census-based stereo matching using FPGA

被引:0
|
作者
Chang, Jiho [1 ]
Choi, Seung Min [1 ]
Lim, Eul-Gyoon [1 ]
Cho, Jae-il [1 ]
机构
[1] Elect & Telecommun Res Inst, Daejeon, South Korea
来源
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON ARTIFICIAL LIFE AND ROBOTICS (AROB 16TH '11) | 2011年
关键词
Stereo matching; Dynamic programming; Census transform;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
The real-time stereo vision is becoming important increasingly in the field of Robotics. It is very difficult to implement the real-time stereo vision system, because it requires very powerful processors. For solving this problem, we present the real-time hardware architecture of the census-based stereo matching IP (Intellectual Property) comprising support-weight and trellis dynamic programming structure. We use census-based cost that is robust for difference in brightness. Using Cost aggregation with support-weight window, our stereo vision system has more robustness for real environment. The stereo matching processor is implemented on a FPGA with the pre-processing part for the rectification and post-processing for reduction of noise. This stereo vision IP is implemented with HDL language and performed up to 30 FPS.
引用
收藏
页码:771 / 774
页数:4
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