A 10-bit 100 MS/s CMOS Current-Steering DAC

A 10-bit, 100MS/s digital-to-analog converter (DAC) is designed in a standard 0.18)tm CMOS process, where a segmented current-steering technique is employed. Through elaborative comparison among different decoding strategies, a "6+4" segmented architecture is used to obtain a balance between area cost and performance. In order for excellent performance, an array of current sources based on a regulated cascode current mirror technique is used to achieve both high output impedance and large-swing output voltage. A latch with functions of amplitude limiting and clock synchronization is employed to reduce glitches and improve dynamic performance. From a single 1.8 V supply, simulation results show that a full-scale current of 8 mA, a differential non-linear (DNL) of +/- 0.1LSB, an integral nonlinear error (INL) of +/- 0.4LSB, and a spurious-free dynamic range (SFDR) of 52dB are achieved.