Analysis and Design of On-Chip Decoupling Capacitors

被引：24

作者：

Charania, Tasreen ^{[1
]}

Opal, Ajoy ^{[1
]}

Sachdev, Manoj ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2013年 / 21卷 / 04期

基金：

加拿大自然科学与工程研究理事会;

关键词：

Decoupling capacitor (decap); integrated circuit (IC) design; power supply noise; LEAKAGE; CIRCUITS; CMOS;

D O I：

10.1109/TVLSI.2012.2198501

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Power supply noise management continues to be a challenge with the scaling of CMOS technologies. Use of on-chip decoupling capacitors (decaps) is the most common noise suppression technique and has significant associated area and leakage costs. There are numerous methods of implementing decaps and it is not always clear which implementation is the most optimal for the given design constraints. This paper characterizes various decap implementations including MOS-based decaps, multilayer metal decaps, and metal-insulatormetal decaps using postlayout simulations in a 65-nm CMOS technology, and provides an outline for determining the most optimal selection and design of decaps based on area, leakage, and location. Hybrid structures are further shown to boost the area efficiency of conventional nMOS decaps by an additional similar to 25%.

引用

页码：648 / 658

页数：11

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