Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

被引：18
作者：
Wu, Tie-Bin [1 ]
Liu, Heng-Zhu [1 ]
Liu, Peng-Xia [1 ]
机构：
[1] Natl Univ Def Technol, Sch Comp Sci, Changsha, Hunan, Peoples R China
来源：
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2013年 / 29卷 / 06期
关键词：
Test data compression; Block merging; Compatibility; Test application time; Code-based testing; PATTERN RUN-LENGTH; TEST DATA VOLUME; REDUCTION; CORES; POWER;
D O I：
10.1007/s10836-013-5415-7
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Growing test data volume and excessive test application time are two serious concerns in scan-based testing for SoCs. This paper presents an efficient test-independent compression technique based on block merging and eight coding (BM-8C) to reduce the test data volume and test application time. Test compression is achieved by encoding the merged blocks after merging consecutive compatible blocks with exact eight codewords. The proposed scheme compresses the pre-computed test data without requiring any structural information of the circuit under test. Therefore, it is applicable for IP cores in SoCs. Experimental results demonstrate that the BM-8C technique can achieve an average compression ratio up to 68.14 % with significant low test application time.
引用
收藏
页码：849 / 859
页数：11
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