Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

被引：8

作者：

Cheng, C. H. ^{[1
]}

Chou, K. I. ^{[2
]}

Chin, A. ^{[2
]}

机构：

[1] Natl Taiwan Normal Univ, Dept Mechatron Technol, Taipei 106, Taiwan

[2] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

来源：

MICROELECTRONIC ENGINEERING | 2013年 / 109卷

关键词：

TiLaO; La2O3; Gate first; Low EOT; LOW-V-T; CMOS;

D O I：

10.1016/j.mee.2013.03.082

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (V-t) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process. (C) 2013 Elsevier B.V. All rights reserved.

引用

页码：35 / 38

页数：4

共 18 条

[1] Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions [J].

Cheng, C. F. ;

Wu, C. H. ;

Su, N. C. ;

Wang, S. J. ;

McAlister, S. P. ;

Chin, Albert .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :333-+

[2] Improved high-temperature leakage in high-density MIM capacitors by using a TiLaO dielectric and an Ir electrode [J].

Cheng, C. H. ;

Pan, H. C. ;

Yang, H. J. ;

Hsiao, C. N. ;

Chou, C. P. ;

McAlister, S. P. ;

Chin, Albert .

IEEE ELECTRON DEVICE LETTERS, 2007, 28 (12) :1095-1097

[3]

Choi K, 2009, 2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P138

[4]

Datta S, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P653

[5]

Huang J, 2009, 2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P34

[6]

LIAO CC, 2008, S VLSI, P190

[7] Low-Threshold-Voltage TaN/LaTiO n-MOSFETs With Small EOT [J].

Lin, S. H. ;

Cheng, C. H. ;

Chen, W. B. ;

Yeh, F. S. ;

Chin, Albert .

IEEE ELECTRON DEVICE LETTERS, 2009, 30 (09) :999-1001

[8] Low-Vt TaN/HfLaO n-MOSFETs Using Low-Temperature Formed Source-Drain Junctions [J].

Lin, S. H. ;

Liu, S. L. ;

Yeh, F. S. ;

Chin, Albert .

IEEE ELECTRON DEVICE LETTERS, 2009, 30 (01) :75-77

[9] A 45nm logic technology with high-k plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging [J].

Mistry, K. ;

Allen, C. ;

Auth, C. ;

Beattie, B. ;

Bergstrom, D. ;

Bost, M. ;

Brazier, M. ;

Buehler, M. ;

Cappellani, A. ;

Chau, R. ;

Choi, C. -H. ;

Ding, G. ;

Fischer, K. ;

Ghani, T. ;

Grover, R. ;

Han, W. ;

Hanken, D. ;

Hatttendorf, M. ;

He, J. ;

Hicks, J. ;

Huessner, R. ;

Ingerly, D. ;

Jain, P. ;

James, R. ;

Jong, L. ;

Joshi, S. ;

Kenyon, C. ;

Kuhn, K. ;

Lee, K. ;

Liu, H. ;

Maiz, J. ;

McIntyre, B. ;

Moon, P. ;

Neirynck, J. ;

Pei, S. ;

Parker, C. ;

Parsons, D. ;

Prasad, C. ;

Pipes, L. ;

Prince, M. ;

Ranade, P. ;

Reynolds, T. ;

Sandford, J. ;

Schifren, L. ;

Sebastian, J. ;

Seiple, J. ;

Simon, D. ;

Sivakumar, S. ;

Smith, P. ;

Thomas, C. .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :247-+

[10] Partial silicides technology for tunable work function electrodes on high-k gate dielectrics -: Fermi level pinning controlled PtSix for HfOx(N) pMOSFET [J].

Nabatame, T ;

Kadoshima, M ;

Iwamoto, K ;

Mise, N ;

Migita, S ;

Ohno, M ;

Ota, H ;

Yasuda, N ;

Ogawa, A ;

Tominaga, K ;

Satake, H ;

Toriumi, A .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :83-86

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