Fully Integrated Doherty Power Amplifier Electromagnetically Optimized in CMOS 65nm with Constant PAE in Backoff

被引：0
|
作者：
Carneiro, Marcos L. [1 ,3 ]
Deltimple, Nathalie [1 ]
Belot, Didier [2 ]
de Carvalho, Paulo H. P. [3 ]
Kerheve, Eric [1 ]
机构：
[1] Univ Bordeaux, IMS Lab, IPB, CNRS,UMR5218, Bordeaux, France
[2] STMicroelect, Crolles, France
[3] Univ Brasilia, Dept Elect Engn, Brasilia, DF, Brazil
来源：
2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2013年
关键词：
D O I：
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中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. Electromagnetic models of each layout path were included in the optimization to dimension circuit components regarding parasitics of an accurate model. The method increased the PAE level in 6% through a constant 8.75 dB backoff range and increased in 2 dB the output power. The amplifier has an output power of 24 dBm, the first PAE peak is 26% and the second one 27%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce the number of inductances and to correctly balance active-loadpull effect. Comparisons were done between schematic, post-layout and electromagnetic simulation.
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页数：4
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