THRU-Based Cascade De-embedding Technique for On-Wafer Characterization of RF CMOS Devices

In this paper, an accurate two-port cascade-based de-embedding technique is presented for characterization of RF devices. It uses two and four structures for device structure with symmetrical and asymmetrical layouts, respectively. Specifically, it outperforms the existing de-embedding techniques by showing distinct capability of accounting for both series contact resistance and distributed effects of interconnects. Furthermore, it is designed to overcome the deficiency of existing transmission line-based techniques in dealing with the interconnects of nonuniform line width. To avoid over de-embedding errors in lumped techniques, the deembedding is performed in unique steps with solely THRU structures for better prediction of test fixture parasitic. The proposed technique is verified on THRU line for a wide frequency range from 2 to 50 GHz. It demonstrates better performance over existing transmission line-based technique as evidenced by excellent agreement with electromagnetic simulation result of THRU line. This is further confirmed by validation result on deembedded gain and gate capacitance of 0.13-mu m nMOS devices.