55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

被引：45

作者：

Kurose, Daisuke ^{[1
]}

Ito, Tomohiko ^{[1
]}

Ueno, Takeshi ^{[1
]}

Yamaji, Takafumi ^{[1
]}

Itakura, Tetsuro ^{[1
]}

机构：

[1] Toshiba Co Ltd, Corp Res & Dev Ctr, Kawasaki, Kanagawa 2128582, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 07期

关键词：

amplifier sharing; analog-to-digital conversion; analog-to-digital converter (ADC); wireless receiver;

D O I：

10.1109/JSSC.2006.873888

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm x 1.4 mm.

引用

页码：1589 / 1595

页数：7

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