Area-Efficient Check Node Unit Architecture for Single Block-Row Quasi-Cyclic LDPC Codes

被引：0

作者：

Zhang, Chuan ^{[1
]}

Weng, Shenghui ^{[1
]}

You, Xiaohu ^{[1
]}

Wang, Zhongfeng ^{[2
]}

机构：

[1] Southeast Univ, Sch Informat Sci & Engn, Natl Mobile Commun Res Lab, Nanjing, Jiangsu, Peoples R China

[2] Broadcom Corp, Irvine, CA 92617 USA

来源：

2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2014年

关键词：

Check node unit; single block-row QC-LDPC codes; hardware efficiency; 2nd minimum search;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are recently proposed. This kind of codes are favorable in applications because of their construction flexibility and good performance compared to PEG codes and array codes. However, the corresponding high row weight will increase the hardware complexity of the check node unit (CNU). In this paper, an area-efficient CNU architecture for single block-row QC-LDPC codes is proposed by refining the searching method for the 2nd minimum. Implementation results of the rate-0.9333 (2115, 1974) code have shown that compared with existing design approaches, the proposed method can achieve at least 15.2% hardware reduction while keeps the latency as the same.

引用

页码：431 / 434

页数：4

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