Challenges in the characterization and modeling of BTI induced variability in Metal Gate/High-k CMOS technologies

被引：0

作者：

Kerber, A. ^{[1
]}

Nigam, T. ^{[2
]}

机构：

[1] GLOBALFOUNDRIES Inc, Technol Reliabil Dev, 1101 Kitchawan Rd, Yorktown Hts, NY 10598 USA

[2] GLOBALFOUNDRIES Inc, Sunnyvale, CA 94085 USA

来源：

2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2013年

关键词：

high-k dielectrics; metal gate; BTI variability; SRAM; CMOS; STACKS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero V-T and Delta V-T and illustrate the minor impact of BTI induced variability on post-stress V-T distributions relevant for modeling the circuit aging.

引用

页数：6

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