The vector fixed point unit of the synergistic processor element of the cell architecture processor

被引:1
|
作者
Mäding, N [1 ]
Leenstra, J [1 ]
Pille, J [1 ]
Sautter, R [1 ]
Büttner, S [1 ]
Ehrenreich, S [1 ]
Haller, W [1 ]
机构
[1] IBM Entwicklung GMBH, Boblingen, Germany
来源
ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2005年
关键词
D O I
10.1109/ESSCIR.2005.1541595
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A Vector Fixed Point Unit (FXU) is designed to speed up multi-media processing. The FXU implements SIMD style integer arithmetic and permute operations. The adder, rotator and permute structure enables the use of static circuits only. The FXU was fabricated using IBM 90nm CMOS SOI technology.
引用
收藏
页码:203 / 206
页数:4
相关论文
共 50 条
  • [11] The use of vector instructions of a processor architecture for emulating the vector instructions of another processor architecture
    Batuzov, K. A.
    PROGRAMMING AND COMPUTER SOFTWARE, 2017, 43 (06) : 366 - 372
  • [12] THE ARCHITECTURE OF THE VAX VECTOR PROCESSOR
    BHANDARKAR, D
    BRUNNER, R
    CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING, 1989, : S15 - S21
  • [13] Power efficient processor architecture and the cell processor
    Hofstee, HP
    11TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 2005, : 258 - 262
  • [14] The Cell processor architecture
    Kahle, J
    MICRO-38: Proceedings of the 38th Annual IEEE/ACM International Symposiumn on Microarchitecture, 2005, : 3 - 3
  • [15] Dual Fixed-Point CORDIC Processor: Architecture and FPGA Implementation
    Jacoby, Andres
    Llamocca, Daniel
    2016 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG16), 2016,
  • [16] Adding a vector unit to a superscalar processor
    Quintana, Francisca
    Corbal, Jesus
    Espasa, Roger
    Valero, Mateo
    Proceedings of the International Conference on Supercomputing, 1999, : 1 - 10
  • [17] Fast and small short vector SIMD matrix multiplication kernels for the synergistic processing element of the CELL processor
    Alvaro, Wesley
    Kurzak, Jakub
    Dongarra, Jack
    COMPUTATIONAL SCIENCE - ICCS 2008, PT 1, 2008, 5101 : 935 - 944
  • [18] Configurable multi-processor architecture and its processor element design
    Nishimura, Tsutomu
    Miki, Takuji
    Sugiura, Hiroaki
    Matsumoto, Yuki
    Kobayashi, Masatsugu
    Kato, Toshiyuki
    Eda, Tsutomu
    Yamauchi, Hironori
    ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 124 - +
  • [19] Scalable GA processor architecture and its implementation of processor-element
    Imai, T
    Yoshikawa, M
    Terai, H
    Yamauchi, H
    2002 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-IV, PROCEEDINGS, 2002, : 3148 - 3151
  • [20] Power-conscious design of the cell processoris synergistic processor element
    Takahashi, O
    Cottier, S
    Dhong, SH
    Flachs, B
    Silberman, J
    IEEE MICRO, 2005, 25 (05) : 10 - 18