High speed low power FEE for silicon detectors in nuclear physics applications

被引：4

作者：

Gomez-Galan, J. A. ^{[1
]}

Lopez-Ahumada, R. ^{[1
]}

Sanchez-Rodriguez, T. ^{[1
]}

Sanchez-Raya, M. ^{[1
]}

Jimenez, R. ^{[1
]}

Martel, I. ^{[2
]}

机构：

[1] Univ Huelva, Dept Ingn Elect Sistemas Informat & Automat, Huelva 21071, Spain

[2] Univ Huelva, Dept Fis Aplicada, Huelva 21071, Spain

来源：

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT | 2013年 / 714卷

关键词：

Front-end electronics; Gain boosting techniques; Silicon detectors; CMOS submicron technology; Noise; FRONT-ENDS; LOW-NOISE; CMOS; PERFORMANCE; TRANSCONDUCTOR; IDENTIFICATION; OPTIMIZATION; GENERATION; DESIGN;

D O I：

10.1016/j.nima.2013.03.002

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A high speed, low power and programmable readout front-end system is presented for silicon detectors to be used in nuclear physics applications. The architecture consists of a folded cascode charge sensitive amplifier, a pole-zero cancellation circuit to eliminate undershoots and a shaper circuit with Gm-C topology. All building blocks include a regulated cascode technique based gain enhancement. Experimental results show that the whole front-end system can be programmed for peaking times of 100 ns, 200 ns and 400 ns maintaining the amplitude of the output voltage. Programmability is achieved by switching different resistors for all poles and zeros. The system has been designed in a 130 nm CMOS technology and powered from a 1.2 V supply. The output pulse has peak amplitude of 200 mV for an input energy of 5 MeV from the detector. A power consumption low noise tradeoff will be considered. (c) 2013 Elsevier B.V. All rights reserved.

引用

页码：155 / 162

页数：8

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