A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications

被引：21

作者：

Cha, Hyouk-Kyu ^{[1
]}

Song, Seong-Sik ^{[2
]}

Kim, Hong-Teuk ^{[2
]}

Lee, Kwyro ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Taejon 305701, South Korea

[2] LG Elect Inst Technol, Seoul 137724, South Korea

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2008年 / 18卷 / 09期

关键词：

ATSC; CMOS; digital TV tuner; harmonic rejection mixer; mismatch calibration;

D O I：

10.1109/LMWC.2008.2002463

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-mu m CMOS technology. Odd harmonic mixing in the 48-862 MHz digital TV frequency band between the input signal and the local oscillator harmonies is a critical problem for direct-conversion receivers which require a harmonic rejection of over -60 dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of -30 to -40 dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than -70 dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.

引用

页码：617 / 619

页数：3

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Narayanaswami, RS ;

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (12) :2003-2015

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