Design of a Low Power Full Adder with a Two Transistor EX-OR Gate Using Gate Diffusion Input of 90 nm

A full adder is the one of the main parts of an arithmetic logic unit (ALU). In this paper a full adder is developed using gate diffusion input (GDI) to perform fast arithmetic operations. The main aim of this paper is the design of a two transistor XOR gate-based full adder using a gate diffusion input (GDI) technique. A two transistor (2T) EX-OR gate is a suitable gate in the design of a full adder. The intention behind the novel method of a 2T EX-OR gate-based full adder design is to reduce power and improve speed in an optimized area with a lower transistor count compared with CMOS technology. A GDI approach is the one of better methods available for the design of digital logic circuits and tends to run the improved conditions. The proposed technique is then applied to a full adder design. The complete work is carried out using the 90 nm technology of a cadence tool to calculate power, delay, and area for the 2T EX-OR gate. The resulting analysis shows that the proposed method is better than conventional CMOS technology.