Reducing test application time for full scan embedded cores

被引：248

作者：

Hamzaoglu, I ^{[1
]}

Patel, JH ^{[1
]}

机构：

[1] Univ Illinois, Ctr Reliable & High Performance Comp, Urbana, IL 61801 USA

来源：

TWENTY-NINTH ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, DIGEST OF PAPERS | 1999年

关键词：

D O I：

10.1109/FTCS.1999.781060

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input. The experimental results for the ISCAS89 circuits showed that PSFS technique significantly reduces both the test application time and the amount of test data for full scan embedded cores.

引用

页码：260 / 267

页数：8

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