Compilation Accelerator on Silicon

被引：1

作者：

Nagarajan, Venkateswaran ^{[1
]}

Srinivasan, Vinesh ^{[1
]}

Kannan, Ramsrivatsa ^{[1
]}

Thinakaran, Prashanth ^{[1
]}

Hariharan, Rajagopal ^{[1
]}

Vasudevan, Bharanidharan ^{[1
]}

Nachiappan, Nachiappan Chidambaram ^{[1
]}

Saravanan, Karthikeyan Palavedu ^{[1
]}

Sridharan, Aswin ^{[1
]}

Sankaran, Vigneshwaran ^{[1
]}

Adhinarayanan, Vignesh ^{[1
]}

Vignesh, V. S. ^{[1
]}

Mukundrajan, Ravindhiran ^{[1
]}

机构：

[1] Waran Res Fdn WARFT, Madras, Tamil Nadu, India

来源：

2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) | 2012年

关键词：

Heterogeneous Multi-Cores; Hardware Compiler; Hardware Scheduler;

D O I：

10.1109/ISVLSI.2012.76

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Current day processors utilize a complex and finely tuned system software to map applications across their cores and extract optimal performance. However with increasing core counts and the rise of heterogeneity among cores, tremendous stress will be exerted on the software stack leading to bottlenecks and underutilization of resources. We propose an architecture for a Compilation Accelerator on Silicon (CAS) coupled with a hardware instruction scheduler to tackle the complexity involved in analyzing dependencies among instructions dynamically, accelerate machine code generation and obtain optimum resource utilization across the cores by effective and efficient scheduling. The CAS is realized as a two-level hierarchical subsystem employing the Primary Compiler on Silicon (PCOS) and Secondary Compiler on Silicon (SCOS) with the hardware instruction scheduler as an integral part of it. A comparative analysis with the conventional GCC compiler is presented for a real world brain modeling application and higher instruction generation rates along with improved scheduling efficiency is observed resulting in a corresponding increase in resource utilization.

引用

页码：267 / 272

页数：6

共 14 条

[1]

Carter L. J., 2002, THESIS U CALIFORNIA

[2]

Govindaraju V, 2011, INT S HIGH PERF COMP, P503, DOI 10.1109/HPCA.2011.5749755

[3]

Kuacharoen P, 2003, ERSA'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS, P95

[4]

Kumar R, 2004, CONF PROC INT SYMP C, P64

[5]

Kumar R, 2003, 36TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, P81

[6]

Kumar S, 2007, CONF PROC INT SYMP C, P162, DOI 10.1145/1273440.1250683

[7]

Mohan A., 2008, THESIS WARAN RES FDN

[8]

Venkateswaran N., 2008, 2008 IEEE International Parallel & Distributed Processing Symposium, P1, DOI 10.1109/IPDPS.2008.4536347

[9]

Venkateswaran N., 2012, ISVLSI

[10]

Venkateswaran N., 2012, FRONTIERS NEUROENERG, V4

← 1 2 →