On-chip split shared data bus architecture for SoC

被引：0
|
作者：
Yang, YS [1 ]
Roh, TM [1 ]
Lee, DW [1 ]
Kwon, WH [1 ]
Kim, J [1 ]
机构：
[1] Elect & Telecommun Res Inst, Basis Res Lab, Taejon 305700, South Korea
来源：
CDES '05: Proceedings of the 2005 International Conference on Computer Design | 2005年
关键词：
on-chip split shared data bus; low power and high speed on-chip bus;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the split shared data bus architecture for SoC. The proposed split shared data bus split one common bus off two buses for decreasing the load capacitance and the critical delay time of the data bus. The power consumption of the proposed split shared data bus for SoC can improve by about 15 similar to 30%, compared with the conventional monolithic shared data bus.
引用
收藏
页码：104 / 108
页数：5
相关论文
共 50 条
  • [41] ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip
    Pasricha, Sudeep
    Dutt, Nikil
    2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 771 - 776
  • [42] Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
    Song, Fenglong
    Fan, Dongrui
    Liu, Zhiyong
    Zhang, Junchao
    Yu, Lei
    Xu, Weizhi
    EURO-PAR 2010 PARALLEL PROCESSING, PT I, 2010, 6271 : 280 - 291
  • [43] Design of the On-chip Bus Based on Wishbone
    Dongye, Changlei
    2011 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL (ICECC), 2011, : 3653 - 3656
  • [44] Design of On-Chip Bus with OCP Interface
    Chang, Chin-Yao
    Chang, Yi-Jiun
    Lee, Kuen-Jong
    Yeh, Jen-Chieh
    Lin, Shih-Yin
    Ma, Jui-Liang
    2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 211 - 214
  • [45] Static Pulsed Bus for on-chip interconnects
    Khellah, M
    Tschanz, J
    Ye, YB
    Narendra, S
    De, VV
    2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2002, : 78 - 79
  • [46] On-chip bus modeling under development
    不详
    ELECTRONIC DESIGN, 1998, 46 (23) : 28 - 28
  • [47] Embedded firewall for on-chip bus transactions
    Lazaro, Jesus
    Bidarte, Unai
    Muguira, Leire
    Astarloa, Armando
    Jimenez, Jaime
    COMPUTERS & ELECTRICAL ENGINEERING, 2022, 98
  • [48] On-chip bus thermal analysis and optimisation
    Wang, F.
    De Bole, M.
    Wu, X.
    Xie, Y.
    Vijaykrishnan, N.
    Irwin, M. J.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (05): : 590 - 599
  • [49] AT LAST, A STANDARD ON-CHIP TEST BUS
    GOSCH, J
    ELECTRONICS, 1988, 61 (16): : 57 - 57
  • [50] MARBLE: an asynchronous on-chip macrocell bus
    Bainbridge, WJ
    Furber, SB
    MICROPROCESSORS AND MICROSYSTEMS, 2000, 24 (04) : 213 - 222
12345