On-chip split shared data bus architecture for SoC

被引：0
|
作者：
Yang, YS [1 ]
Roh, TM [1 ]
Lee, DW [1 ]
Kwon, WH [1 ]
Kim, J [1 ]
机构：
[1] Elect & Telecommun Res Inst, Basis Res Lab, Taejon 305700, South Korea
来源：
CDES '05: Proceedings of the 2005 International Conference on Computer Design | 2005年
关键词：
on-chip split shared data bus; low power and high speed on-chip bus;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the split shared data bus architecture for SoC. The proposed split shared data bus split one common bus off two buses for decreasing the load capacitance and the critical delay time of the data bus. The power consumption of the proposed split shared data bus for SoC can improve by about 15 similar to 30%, compared with the conventional monolithic shared data bus.
引用
收藏
页码：104 / 108
页数：5
相关论文
共 50 条
  • [21] A Shared-Way Set Associative architecture for on-chip caches
    Hamkalo, JL
    Djordjalian, A
    Cernuschi-Frías, B
    COMPUTERS AND THEIR APPLICATIONS, 2001, : 125 - 128
  • [22] Enhanced Overloaded CDMA Interconnect (OCI) Bus Architecture for on-Chip Communication
    Ahmed, Khaled E.
    Farag, Mohammed M.
    PROCEEDINGS 2015 IEEE 23RD ANNUAL SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS - HOTI 2015, 2015, : 78 - 87
  • [23] Pipelined on-chip bus architecture with distributed self-timed control
    Plosila, J
    Liljeberg, P
    Isoaho, J
    SCS 2003: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, 2003, : 257 - 260
  • [24] Parallel Overloaded CDMA Interconnect (OCI) Bus Architecture for On-Chip Communications
    Ahmed, Khaled E.
    Farag, Mohammed M.
    2015 IEEE CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), 2015, : 621 - 624
  • [25] Process variations aware robust on-chip bus architecture synthesis for MPSoCs
    Pandey, Sujan
    Drechsler, Rolf
    Murgan, Tudor
    Glesner, Manfred
    PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2989 - 2992
  • [26] An alternative architecture for on-chip global interconnect: Segmented bus power modeling
    Zhang, Y
    Ye, W
    Irwin, MJ
    CONFERENCE RECORD OF THE THIRTY-SECOND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 1062 - 1065
  • [27] Specification of an asynchronous on-chip bus
    Plosila, J
    Seceleanu, T
    FORMAL METHODS AND SOFTWARE ENGINEERING, PROCEEDINGS, 2002, 2495 : 383 - 395
  • [28] A Theoretical analysis of Fibonacci coding techniques on On-chip Data Bus
    Sathish, Anchula
    Niharika, Panyam Ranga Reddy
    INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING TECHNOLOGIES AND APPLICATIONS (ICACTA), 2015, 45 : 533 - 539
  • [29] An efficient switching activity reduction technique for on-chip data bus
    Sathish, A.
    Madhavi Latha, M.
    Lalkishor, K.
    International Journal of Computer Science Issues, 2011, 8 (4 4-2): : 407 - 413
  • [30] CoreConnect: The on-chip bus system
    Weiss, R
    ELECTRONIC DESIGN, 2001, 49 (07) : 110 - 111
12345