On-chip split shared data bus architecture for SoC

被引：0

作者：

Yang, YS ^{[1
]}

Roh, TM ^{[1
]}

Lee, DW ^{[1
]}

Kwon, WH ^{[1
]}

Kim, J ^{[1
]}

机构：

[1] Elect & Telecommun Res Inst, Basis Res Lab, Taejon 305700, South Korea

来源：

CDES '05: Proceedings of the 2005 International Conference on Computer Design | 2005年

关键词：

on-chip split shared data bus; low power and high speed on-chip bus;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the split shared data bus architecture for SoC. The proposed split shared data bus split one common bus off two buses for decreasing the load capacitance and the critical delay time of the data bus. The power consumption of the proposed split shared data bus for SoC can improve by about 15 similar to 30%, compared with the conventional monolithic shared data bus.

引用

页码：104 / 108

页数：5

共 3 条

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Lu, HI
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Hsieh, CT
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[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2002, 21 (04) : 408 - 414
[3] Bus architecture of a system on a chip with user-configurable system logic
Winegarden, S
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (03) : 425 - 433

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