Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function

被引:33
作者
Hikawa, Hiroomi [1 ]
Maeda, Yutaka [1 ]
机构
[1] Kansai Univ, Dept Engn, Osaka 5648680, Japan
关键词
Field-programmable gate array (FPGA); hardware; neighborhood function; self-organizing map (SOM); IP CORE; IMPLEMENTATION; PARALLEL; ARCHITECTURE;
D O I
10.1109/TNNLS.2015.2398932
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Many self-organizing maps (SOMs) implemented on hardware restrict their neighborhood function values to negative powers of two. In this paper, we propose a novel hardware friendly neighborhood function that is aimed to improve the vector quantization performance of hardware SOM. The quantization performance of the hardware SOM with the proposed neighborhood function is examined by simulations. Simulation results show that the proposed function can improve the hardware SOM's vector quantization capability even though the function value is restricted to negative powers of two. Then, the hardware SOM is implemented on field-programmable gate array to find out the hardware cost and performance speed of the proposed neighborhood function. Experimental results show that the proposed neighborhood function can improve SOM's quantization performance without additional hardware cost or slowing down the operating speed. Due to fully parallel operation, the proposed SOM with 16 x 16 neurons achieves a performance of 25 344 million connections updates per second.
引用
收藏
页码:2861 / 2873
页数:13
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