New Test Compression Scheme Based on Low Power BIST

被引：0

作者：

Tyszer, J. ^{[1
]}

Filipek, M. ^{[1
]}

Mrugalski, G. ^{[2
]}

Mukherjee, N. ^{[2
]}

Rajski, J. ^{[2
]}

机构：

[1] Poznan Univ Tech, PL-60965 Poznan, Poland

[2] Mentor Graphics Corp, Wilsonville, OR 97070 USA

来源：

2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS 2013) | 2013年

关键词：

Built-in self-test; hybrid low power compression; low power test; test data compression; scan-based test; toggling; SCAN; LFSR; DISSIPATION; GENERATION; PATTERNS; ATPG; TPG;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

引用

页数：6

共 41 条

[1]

[Anonymous], 2005, P ITC

[2] Extending OPMISR. beyond 10x scan test efficiency [J].

Barnhart, C ;

Brunkhorst, V ;

Distler, F ;

Farnsworth, O ;

Ferko, A ;

Keller, B ;

Scott, D ;

Koenemann, B ;

Onodera, T .

IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (05) :65-73

[3] Reducing test data volume using external/LBIST hybrid test patterns [J].

Das, D ;

Touba, NA .

INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, :115-122

[4] Tailoring ATPG for embedded testing [J].

Dorsch, R ;

Wunderlich, HJ .

INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, :530-537

[5] Low Power Decompressor and PRPG with Constant Value Broadcast [J].

Filipek, Michal ;

Fukui, Yoshiaki ;

Iwata, Hiroyuki ;

Mrugalski, Grzegorz ;

Rajski, Janusz ;

Takakura, Masahiro ;

Tyszer, Jerzy .

2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, :84-89

[6]

Gerstendorfer S., 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), P77, DOI 10.1109/TEST.1999.805616

[7]

Gherman V, 2004, INT TEST CONF P, P48

[8]

Girard P, 2010, POWER-AWARE TESTING AND TEST STRATEGIES FOR LOW POWER DEVICES, P1, DOI 10.1007/978-1-4419-0928-2

[9] A modified clock scheme for a low power BIST test pattern generator [J].

Girard, P ;

Guiller, L ;

Landrault, C ;

Pravossoudovitch, S ;

Wunderlich, HJ .

19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2001, :306-311

[10]

Hakmi A.-W., 2007, P ITC

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