DPWM time resolution requirements for digitally controlled DC-DC converters

被引：0

作者：

Chen, JQ ^{[1
]}

Ribeiro, M ^{[1
]}

Payseo, R ^{[1
]}

Zhou, DS ^{[1
]}

Smith, JR ^{[1
]}

Kernahan, K ^{[1
]}

机构：

[1] FyreStorm Inc, 255 San Geronimo Way, Sunnyvale, CA 94085 USA

来源：

APEC 2006: TWENTY-FIRST ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, VOLS 1-3 | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Digitally controlled dc-dc converters can exhibit undesired limit-cycle oscillations due to the lack of time resolution in the digital pulse-width modulator (DPWM) to satisfy specified output voltage regulation accuracy In this paper, the relationship between DPWM time resolution and output voltage regulation accuracy is studied for several basic converters operating in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The minimum DPWM time resolution required to prevent limit-cycle oscillations is then derived. Cycle-Skip, a technique for adjusting the swiching frequency and on-lime without load current sensing, is proposed to improve the output voltage regulation accuracy and lower DPWM resolution requirements. Experimental results are provided to validate the theoretical analysis and the effectiveness of the Cycle-Skip technique in avoiding limit-cycle oscillations.

引用

页码：1127 / 1132

页数：6

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