A HIGH SPEED LOW POWER LATCHED COMPARATOR FOR SHA-LESS PIPELINED ADC

被引：2

作者：

Zhao, Lei ^{[1
]}

Yang, Yintang ^{[1
]}

Zhu, Zhangming ^{[1
]}

机构：

[1] Xidian Univ, Inst Microelect, Xian 710071, Peoples R China

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2013年 / 22卷 / 03期

关键词：

Latched comparator; high-speed; low dissipation; pipelined ADC;

D O I：

10.1142/S0218126613500047

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 mu W at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-mu m 3.3V BiCMOS technology.

引用

页数：9

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