Nanomanufacturing Strategy for Aligned Assembly of Nanowire Arrays

被引:1
作者
Shin, Kyeong-Sik [1 ]
Chui, Chi On [1 ,2 ]
机构
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
[2] Univ Calif Los Angeles, Calif NanoSyst Inst, Los Angeles, CA 90095 USA
关键词
Alignment; assembly; crystallographic etching; line edge roughness; nanostructure array; nanowire; WALLED CARBON NANOTUBES; LABEL-FREE DETECTION; GROWTH; ELECTRONICS; TRANSISTORS; DNA;
D O I
10.1007/s11664-012-2058-x
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The work reported here concerns a proposed nanomanufacturing strategy to assemble aligned quasi-one-dimensional nanostructure arrays with intrinsic and concurrent control over the resultant number, pitch, and linewidth. For the first time, a standard lithography and crystallographic etching approach have been combined to synthesize periodic, sublithographic, and line edge roughness (LER)-free surface arrays for selective conjugation of nanowires. Key experimental modules have been developed, including the formation of LER-free substrate arrays, formation of periodically dissimilar surfaces, selective conjugation of nanowires, and stamping transfer of nanowire arrays. In particular, successful assembly of Si nanowires onto periodic Si/SiO (x) surfaces and subsequent transfer of the resultant aligned Si nanowire arrays onto a different substrate surface have been repeatedly demonstrated. The dependences and probability of nanowire aligned assembly have also been examined. The proposed strategy is based on a wafer-scale and very large-scale integration (VLSI)-compatible philosophy, and alignment to pre-existing features on the target substrate is also inherently allowed as a side benefit. Besides, LER-free features could be created, which arguably enables extreme linewidth scaling with suppressed variations.
引用
收藏
页码:935 / 943
页数:9
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