A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

被引：15

作者：

Mochizuki, Seiji ^{[1
]}

Shibayama, Tetsuya ^{[1
]}

Hase, Masaru ^{[1
]}

Izuhara, Fumitaka ^{[1
]}

Akie, Kazushi ^{[1
]}

Nobori, Masaki ^{[1
]}

Imaoka, Ren ^{[1
]}

Ueda, Hiroshi ^{[1
]}

Ishikawa, Kazuyuki ^{[1
]}

Watanabe, Hiromi ^{[1
]}

机构：

[1] Renesas Technol Corp, Tokyo 1878588, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 11期

关键词：

Clock gating; high picture quality; H.264 video codec; low power consumption; mobile application; MPEG-4 video codec;

D O I：

10.1109/JSSC.2008.2004534

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed an H.264/MPEG-4 dual video codec IP for mobile applications such as digital still cameras (DSCs), digital video cameras (DVCs), and mobile phones. The codec is capable of encoding and decoding HD-sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD-sized pictures at 54 MHz. We have implemented our original architecture based on a macroblock-level pipeline method and encoding algorithms suitable for the architecture in the codec, which enable low power of 64 mW for HD encoding with high picture quality equivalent to that of the H.264 reference encoder "JM (Joint Model)".

引用

页码：2354 / 2362

页数：9