Two-dimensional numerical analysis of nanoscale junctionless and conventional Double Gate MOSFETs including the effect of interfacial traps

被引：17
作者：
Chebaki, Elasaad [1 ]
Djeffal, Faycal [1 ]
Bentrcia, Toufik
机构：
[1] Univ Batna, Dept Elect, LEA, Batna 05000, Algeria
来源：
PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 9, NO 10-11 | 2012年 / 9卷 / 10-11期
关键词：
junctionless; traps; numerical analysis; DG MOSFET; nanoscale; DESIGN;
D O I：
10.1002/pssc.201200128
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This paper deals with the immunity behavior of the junctionless DG MOSFET device against the hot carrier degradation effect. The junctionless device is highly privileged because of its easy fabrication procedure, homogeneity along the channel axe in addition to its promising electrical characteristics compared to the conventional DG MOSFET with PN junction at the source and the drain sides. As a result, we demonstrate that junctionless DG MOSFET can be a viable option to enhance the immunity performances of nanoscale CMOS-based devices technology for nanoelectronics digital applications. (C) 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
引用
收藏
页码：2041 / 2044
页数：4
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