An 11-Bit 10 MS/s SAR ADC with C-R DAC Calibration and Comparator Offset Calibration

An 11-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for low-power and small-area applications. A 10-bit differential capacitor-resistor (C-R) digital-to-analog converter (DAC) is used to minimize the area of a DAC. The use of a C-R DAC reduces the capacitor area of a SAR ADC used CDAC by 75%. A capacitor calibration for the upper 5-bit capacitors of the C-R DAC is proposed to increase the linearity of the C-R DAC. To evaluate the proposed SAR ADC, an 11-bit 10 MS/s SAR ADC is implemented using a 180 nm 1-poly six-metal CMOS process with a supply of 1.8 V. The proposed SAR ADC has an effective number of bits (ENOBs) of 10.3 bits at a sampling rate of 10 MS/s for a 3.6-Vpp differential sinusoidal analog input with a frequency of 4.789 MHz. The measured ENOBs is 10.45 bits when the frequency of the analog input signal is 42.39 kHz. The proposed C-R DAC calibration including comparator offset calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity (INL) from -1/ +1.26 LSBs and -1.98/+1.96 LSBs to -0.97/ +0.85 LSBs and -0.79/ +0.83 LSBs, respectively.