Partitioning and Dynamic Mapping Evaluation for Energy Consumption Minimization on NoC-Based MPSoC

被引：0

作者：

Antunes, Eduardo ^{[1
]}

Soares, Matheus ^{[1
]}

Aguiar, Alexandra ^{[1
]}

Johann, Sergio F. ^{[1
]}

Sartori, Marcos ^{[1
]}

Hessel, Fabiano ^{[1
]}

Marcon, Cesar ^{[1
]}

机构：

[1] PUCRS Pontif Univ Catholic Rio Grande Sul, PPGCC Postgrad Prog Comp Sci, Porto Alegre, RS, Brazil

来源：

2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) | 2012年

关键词：

Partitioning; Mapping; MPSoC; NoC;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Software complexity has increased considerably over recent years, needing special target architectures as NoC-based MPSoCs to fulfill the heavy storage, communication and computation requirements. The design of these systems requires efficient methodologies aggregating partitioning and mapping. In these sense, this paper explores partitioning and mapping influence on energy consumption of homogeneous NoC-Based MPSoC. In addition, it compares two strategies to achieve efficient dynamic mappings: one that map tasks directly onto processors and another one that applies a previous static task-partitioning and uses this information to choose the dynamic task mapping. Experiments with various synthetic and four embedded applications show the efficiency of the second strategy that minimizes an average of 23.5% on energy consumption.

引用

页码：451 / 457

页数：7

共 21 条

[1] [Anonymous], 1996, Standard Mathematical Tables and Formulae
[2] Bononi L, 2007, DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, P543, DOI 10.1109/DSD.2007.4341521
[3] Contention-aware Application Mapping for Network-on-Chip Communication Architectures
Chou, Chen-Ling
Marculescu, Radu
[J]. 2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2008, : 164 - 169
[4] Dynamic Task Mapping for MPSoCs
de Souza Carvalho, Ewerson Luiz
Vilar Calazans, Ney Laert
Moraes, Fernando Gehm
[J]. IEEE DESIGN & TEST OF COMPUTERS, 2010, 27 (05): : 26 - 35
[5] A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip
Goehringer, Diana
Huebner, Michael
Benz, Michael
Becker, Juergen
[J]. 2010 18TH IEEE ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2010), 2010, : 259 - 262
[6] Guang Sun, 2010, Proceedings 2010 International Symposium on System-on-Chip - SOC, P8, DOI 10.1109/ISSOC.2010.5625542
[7] Energy-aware mapping for tile-based NoC architectures under performance constraints
Hu, JC
Marculescu, R
[J]. ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 233 - 239
[8] Jalier C, 2010, DES AUT TEST EUROPE, P184
[9] OPTIMIZATION BY SIMULATED ANNEALING
KIRKPATRICK, S
GELATT, CD
VECCHI, MP
[J]. SCIENCE, 1983, 220 (4598) : 671 - 680
[10] Kun-Lin Tsai, 2010, 2010 8th IEEE International NEWCAS Conference (NEWCAS 2010), P257, DOI 10.1109/NEWCAS.2010.5603934

← 1 2 3 →