Analysis of hot-electron reliability and device performance in 80-nm double-gate SOI n-MOSFET's

In this paper, we employ a comprehensive Monte Carlo-based simulation method to model hot-electron injection, to predict induced device degradation, and to simulate and compare the performance of two double-gate fully depicted silicon-on-insulator n-MOSFET's tone with a lightly-doped channel and one with a heavily-doped channel) and a similar lightly-doped single-gate design. All three designs have an effective channel length of 80 nm and a silicon layer thickness of 25 nm, Monte Carlo simulations predict a spatial retardation between the locations of peak hot-electron injection into the front and back oxides, Since the observed shift is a significant portion of the channel length, the retardation effect greatly influences induced degradation in otherwise well-designed SOI devices, This effect may signal an important consideration fur sub-100-nm design strategy. Simulations were also conducted to compare transistor performance against a key figure of merit. Evaluation of reliability and performance results indicate that the double-gate design with a lightly doped channel offers the best tradeoff in immunity to hot-electron-induced degradation and performance.