Efficient architectures for modulo 2n-2 arithmetic units

被引:1
作者
Vassalos, Evangelos [1 ]
Bakalis, Dimitris [1 ]
机构
[1] Univ Patras, Dept Phys, Elect Lab, GR-26110 Patras, Greece
关键词
modulo multiplier; digital signal processing; modulo squarer; modulo arithmetic; residue number system; multi-operand modulo adder; RESIDUE NUMBER SYSTEM; BINARY CONVERTER; DESIGN; IMPLEMENTATION;
D O I
10.1080/00207217.2015.1020528
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Moduli of the 2(n) and 2(n)+/- 1 forms are usually employed in designs that adopt the residue number system. However, in several cases such as in finite impulse response filters and communication components, a modulo value equal to 2(n)-2 can be used. So far, modulo 2(n)-2 arithmetic units have been based either on look-up tables or on generic modulo arithmetic units. In this work, by taking advantage of the properties of modulo 2(n)-2 arithmetic, we propose efficient modulo 2(n)-2 multi-operand adder, multiplier as well as squarer architectures. The proposed circuits are based on the corresponding ones for modulo 2(n)(-1)-1 arithmetic and some simple logic. Experimental results validate that the proposed circuits achieve significant area and delay savings compared to those previously presented.
引用
收藏
页码:2062 / 2074
页数:13
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