Design and Implementation of 64-kb CMOS Static RAMs for Josephson-CMOS Hybrid Memories

We are developing a Josephson-CMOS hybrid memory, which enables subnanosecond access time, to overcome a memory bottleneck in single-flux-quantum digital systems. In this study, we designed and examined 64-kb CMOS static RAMs for realizing fully functional hybrid memories. The designed CMOS static RAM is composed of an eight-transistor SRAM cell array, address decoders, and CMOS differential amplifiers. The differential amplifiers can amplify 40-mV input signals from Josephson latching drivers to CMOS voltage levels at high speed. The total number of the differential amplifiers is 21, which are used for an 8-bit word address, a 3-bit block address, 2-bit read/write control signals and 8-bit data inputs. The 64-kb CMOS static RAM was fabricated by using a 0.18 mu m CMOS process. We confirmed fully functional read and write operations for all addresses. The access time was evaluated to be 1.34 ns at 4.2 K. The power consumption was estimated to be 27.5 mW for read operation and 41.0 mW for write operation at 1 GHz. The 64-kb CMOS static RAM was combined with a Josephson chip, which includes single-flux-quantum serial-parallel converters and arrays of Josephson latching drivers, with a piggyback configuration. We partly confirmed the correct operation of the 64-kb hybrid memory for limited address.