Design and characterization of a 10 Gb/s clock and data recovery circuit implemented with phase-locked loop

被引：10
作者：
Song, JH [1 ]
Yoo, TW [1 ]
Ko, JH [1 ]
Park, CS [1 ]
Kim, JK [1 ]
机构：
[1] ETRI, Opt Commun Dept, Taejon, South Korea
来源：
ETRI JOURNAL | 1999年 / 21卷 / 03期
关键词：
D O I：
10.4218/etrij.99.0199.0301
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A clock and data recovery circuit with a phase-locked Loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency- and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to 60 degrees C and showed no increase of error, This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.
引用
收藏
页码：1 / 5
页数：5
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