Plasma charging damage in deep-submicron CMOS technology and beyond

被引：0

作者：

Cheung, KP ^{[1
]}

机构：

[1] Rutgers State Univ, Dept Elect & Comp Engn, Piscataway, NJ 08855 USA

来源：

SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Plasma charging damage in CMOS technology is reviewed. The gate-oxide thickness dependent sensitivity to charging damage is examined. Ultra thin gate-oxide can tolerate low to moderate charging stress at room temperature better than thicker oxide, but not at elevated temperature. When the charging stress level is high, gate-oxide reliability degradation will result regardless the stress temperature, When high-k dielectric replaces SiO2 as gate-dielectric, plasma charging damage should become very severe again.

引用

页码：315 / 320

页数：6

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