Novel Design Method for Electrically Symmetric High-Q Inductor Fabricated Using Wafer-Level CSP Technology

被引：1

作者：

Aoki, Yutaka ^{[1
]}

Shimizu, Shoichi ^{[2
]}

Honjo, Kazuhiko ^{[2
]}

机构：

[1] CASIO Comp Co Ltd, Tokyo 2058555, Japan

[2] Univ Electrocommun, Grad Sch Informat & Engn, Tokyo 1820021, Japan

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2013年 / 3卷 / 01期

关键词：

Inductance; inductor; Q-factor; redistribution; wafer-level chip-size package (WLP);

D O I：

10.1109/TCPMT.2012.2226722

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

High-Q spiral inductors are described that are embedded in the wafer-level chip-size package (WLP) and suffer from unfavorable two-port asymmetric characteristics. To solve this problem, a novel clip-type inductor is proposed, where an electrode crossover point in multiturn inductor structures is modified from a conventional mirror symmetric point to a novel electrical symmetric point. These novel clip-type inductors are designed and fabricated using the WLP technology. By means of a developed 4 nH novel clip inductor, a Q factor value difference between the two ports can be significantly reduced to 1.4% from 14.8% at 1.4 GHz. The Q factors of developed inductors are evaluated under both a conventional shortcircuited load condition and an impedance-matched condition. In addition, a novel evaluation method for inductance values for inductors is also described. By using newly derived formulas, inductance values for a fabricated WLP clip-type inductor and a fabricated meander-type inductor are evaluated. This method represents the inherent nature of inductor devices under test including circuit parasitic elements.

引用

页码：31 / 39

页数：9

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