Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors

被引：86

作者：

Park, Sangyoung ^{[1
]}

Park, Jaehyun ^{[1
]}

Shin, Donghwa ^{[2
]}

Wang, Yanzhi ^{[3
]}

Xie, Qing ^{[3
]}

Pedram, Massoud ^{[3
]}

Chang, Naehyuck ^{[1
]}

机构：

[1] Seoul Natl Univ, Seoul 151744, South Korea

[2] Politecn Torino, I-10129 Turin, Italy

[3] Univ So Calif, Los Angeles, CA 90089 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2013年 / 32卷 / 05期

基金：

美国国家科学基金会; 新加坡国家研究基金会;

关键词：

Delay and energy overhead; dynamic voltage and frequency scaling (DVFS); macromodel; POWER MANAGEMENT; DC;

D O I：

10.1109/TCAD.2012.2235126

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Dynamic voltage and frequency scaling (DVFS) has been studied for well over a decade. Nevertheless, existing DVFS transition overhead models suffer from significant inaccuracies; for example, by incorrectly accounting for the effect of DC-DC converters, frequency synthesizers, voltage, and frequency change policies on energy losses incurred during mode transitions. Incorrect and/or inaccurate DVFS transition overhead models prevent one from determining the precise break-even time and thus forfeit some of the energy saving that is ideally achievable. This paper introduces accurate DVFS transition overhead models for both energy consumption and delay. In particular, we redefine the DVFS transition overhead including the underclocking-related losses in a DVFS-enabled microprocessor, additional inductor IR losses, and power losses due to discontinuous-mode DC-DC conversion. We report the transition overheads for a desktop, a mobile and a low-power representative processor. We also present DVFS transition overhead macromodel for use by high-level DVFS schedulers.

引用

页码：695 / 708

页数：14

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